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high probable CV1K D backwards compatible with B games
maybe, if I recall CV1K B includes an RTC where it also stores high-scores and settings (hence the coin cell battery on B boards) CV1K D has more memory but dropped the RTC and stores settings on the Flash ROM itself.

so it really comes down to if B games are ok with the RTC not being present, and even if they are you'll lose the functionality of settings and scores getting stored. Also Ibara has a clock in-game that reads from the RTC (not sure if other games do also).

a universal board would really be a CV1K B with larger memory.
 
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maybe, if I recall CV1K B includes an RTC where it also stores high-scores and settings (hence the coin cell battery on B boards) CV1K D has more memory but dropped the RTC and stores settings on the Flash ROM itself.
Cv1000-D has this chip too. Its at U10 which I think all cv1k-d games populate.

They dont however have battery backup for the rtc, so they just have access to the eeprom part of it, and I guess the RTC will be reset each boot.
 
maybe, if I recall CV1K B includes an RTC where it also stores high-scores and settings (hence the coin cell battery on B boards) CV1K D has more memory but dropped the RTC and stores settings on the Flash ROM itself.

so it really comes down to if B games are ok with the RTC not being present, and even if they are you'll lose the functionality of settings and scores getting stored. Also Ibara has a clock in-game that reads from the RTC (not sure if other games do also).

a universal board would really be a CV1K B with larger memory.
If I had to guess, I'd bet that RTC has something to do with rank timer too.
 
a universal board would really be a CV1K B with larger memory
but... CV1K D is in fact a CV1K B with larger memory ;)

and that's the only possible problem I may imagine, because "larger memory" is not that simple in SDRAM world, and may require a bit different SH3's SDRAM controller configuration.
 
but... CV1K D is in fact a CV1K B with larger memory ;)

and that's the only possible problem I may imagine, because "larger memory" is not that simple in SDRAM world, and may require a bit different SH3's SDRAM controller configuration.
So is this the Naomi 2 of Cv1ks?
 
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