There is a plan for a CPS1 FPGA core early 2020 by jotego. Right now he is slowly releasing earlier Capcom arcade cores documenting the evolution and there is a pretty good chance that the custom is implemented in FPGA. Unsure if gate level modelling? would be his goal since that will require decapping, but should be cycle accurate eventually (like MegaSD no more no less).I'm hoping as part of this that the A custom can be documented for potential reproduction. It was used on CPS2 as well as CPS1